The present invention relates to a logic circuit and, more particularly, to a logic circuit used in a latch circuit operative at a low power supply voltage of 1 v or less.
A conventional logic circuit of this type is generally constituted by a CMOS logic block circuit, and an example is shown in FIG. 12. In this example, logic elements such as an inverter INV1, NAND gates NAND1, . . . , and an inverter INV2 are connected to power lines V.sub.DD and V.sub.ss through switching transistors M1, M2, . . . , M3 and switching transistors M4, M5, . . . , M6. With this arrangement, a control signal CSB of high level and a control signal CS of low level are supplied to the switching transistors M1, M2, . . . , M3 and the switching transistors M4, M5, . . . , M6, respectively, to control the operations of the respective logic elements.
Since the switching transistors used in this arrangement, however, are arranged as transistors having a single threshold voltage, the following problems are posed.
For example, assume an operation using a dry cell. When the power supply voltage of this logic circuit is decreased from 5 V (conventional case) to 1 V, the threshold voltage of each transistor comes close to the power supply voltage in an ON state (CS=HIGH and CSB=LOW), and the transconductance of each transistor becomes extremely small to undesirably prolong the delay time of each logic circuit element. When the threshold voltage of each transistor constituting the logic circuit is decreased, a leakage current is increased in an OFF state (CS=LOW and CSB=HIGH), and the endurance of the dry cell is greatly shortened. In addition, the control transistors are rendered nonconductive, and therefore storage information is destroyed.